This invention relates to the electrical interconnection of various active devices in an integrated circuit on a semiconductor chip; and more particularly, to the formation of electrical contacts to regions at the surface of a semiconductor substrate which are doped opposite to the substrate. One such electrical contact which is widely used in the prior art is illustrated in FIGS. 1A and 1B.
In those Figures, reference numeral 10 indicates a P-type semiconductor substrate; reference numeral 11 indicates the substrate's surface; and reference numeral 12 indicates two N-type doped regions at the substrate's surface to which electrical contact is to be made. Regions 12 form the source and drain of a field-effect transistor 13.
Transistor 13 has a gate 14 which lies on an insulating layer 15. Another insulating layer 16 defines the outer perimeter of the transistor. And still another insulating layer 17 overlies the entire transistor except in those areas where electrical contact is to be made to the N-type doped regions. During fabrication, insulating layer 17 is initially formed over the entire chip; and thereafter, openings 18 are etched in it where electrical contacts are to be made.
A plurality of patterned metal conductors 19 lie on insulating layer 18 and selectively make contact to the N-type regions 12 through the openings 18. In patterning those conductors, it is highly desirable to make them as narrow as possible and to space them as close to each other as possible, in order to maximize the number of interconnections which can be made in any given area. However, a problem occurs where the conductors make contact to the N-type regions.
There, the conductors 19 must be widened from whatever minimum dimension that is possible to achieve in a given fabrication process, in order to ensure that they will completely fill the openings 18. For example, suppose that minimal dimension which can be fabricated is "L". Then, the holes 18 would be fabricated to be as small as L.times.L; and the conductors 19 would be enlarged to L+2.epsilon. around the hole. Also, any conductor which ran alongside of a hole would have to be spaced from the enlarged conductor portion by the minimal dimension L.
Actual values for L and .epsilon. will, of course, depend upon the particular fabrication process. But as one typical example, L and .epsilon. could respectively equal 2.0 um and 0.5 um. In any case, it is clear that an increased number of interconnections could be made in a given area if the extra conductor width .epsilon. could be eliminated from around the holes 18.
Various problems, however, exist with making the conductors 19 the same size as the hole 18. Due to misalignment tolerances, the conductors 19 could be offset from the holes 18. As a result, when the conductors 19 are patterned, a portion of the N-type regions 12 will be exposed. Consequently, the regions 12 can be contaminated with various impurities. These impurities may come, for example, from the surrounding air, or from the etchant that is used to pattern the conductors. Also, if a plasma etch is used, the surface of the N-type regions will be damaged by the impinging plasma ions.
Often, the conductors 19 are comprised of a metal having some silicon in it. The silicon is included to enhance the formation of a metal-silicon alloy at the surface of the N-type regions. When such metals are patterned however, thousands of small silicon particles are left on the surface of insulating layer 17 after the metal etch; and these must be removed with another etchant that attacks silicon. However, if portions of the N-type silicon regions 12 are exposed, those exposed portions will also be attacked by the etchant. This problem has been handled by making the N-type regions 12 very deep so that the silicon etchant will not go completely through them. But deep N-type regions are not desirable because they give rise to a large X.sub.j parameter; and thus transistors with short channel lengths cannot be fabricated.
Accordingly, a primary object of the invention is to provide an improved electrical contact to a region of a semiconductor substrate which is doped opposite to the substrate.
Another object is to provide an electrical contact through a hole in an insulating layer on a semiconductor substrate which only partially fills the hole.
Still another object is to provide a method of making an electrical contact which fulfills the above two objectives.